1. Field
This disclosure relates generally to memories, and more specifically, to split gate memory cells with improved erase performance.
2. Related Art
Split gate non-volatile memories (NVMs) including, for example, split gate flash devices, provide advantages over single-transistor stacked-gated devices such as a control gate over a floating gate. They are particularly useful in the case of the storage element layer being much thinner than the typical floating gate. One type of storage layer that offers benefits is a layer of nanocrystals. A split gate NVM can allow a wider read window because it allows the erased state (typically the low threshold voltage (Vt) state) to be near or below zero Volts. The select transistor in series with the charge storage transistor is able to keep the bitcell “off” when it is unselected and the charge storage transistor's Vt is near or less than zero Volts. This cannot be done in a single transistor NVM because if it has a low or negative threshold it will be conducting or leaking when it is unselected. So, a split gate bitcell can permit a larger read window because it allows the erased Vt to be low.
When erase of a nanocrystal bitcell is accomplished by Fowler-Nordheim (FN) tunneling, the erased Vt will usually saturate when the number of electrons tunneling out of the nanocrystals through one dielectric is balanced by electrons tunneling onto the nanocrystals through another dielectric. When erase is performed by FN tunneling of electrons through the oxide between the nanocrystals and the overlying control gate (top oxide), eventual saturation of erase will occur when FN tunneling of electrons from the substrate to the nanocrystals occurs through the bottom oxide. The conduction of electrons from the substrate to the nanocrystals during erase is referred to as back injection. Erase saturation occurs because the electric fields in the two dielectrics become equal near the end of erase, thus FN tunneling becomes the same in both dielectrics. This erase saturation limits the Vt window of the bitcell. When the Vt window of the bitcell is limited, the useful life of the memory suffers, because it becomes increasingly difficult for the circuitry to correctly sense a programmed or erased bitcell as other mechanisms shift the Vt of the bitcells from their original programmed or erased states.
It is therefore desirable to provide split NVM with nanocrystals with an enlarged window of threshold voltage and rapid erase capability.